Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology require ever increasing clock rates and memory bus widths to achieve high data rates. These high data rates, however, are subject to practical limitations. An optimal memory circuit designed for a normal range of supply voltage and temperature may fail to operate correctly under high voltage and high temperature conditions required by a burn in test. A memory circuit functioning at a normal high voltage and high temperature limit of 3.6 V and 90.degree. C., for example, may fail to operate at a burn in condition of 6.5 V and 125.degree. C.
A particular failure mode occurs when a word line is activated and initial data from a memory cell is applied to complementary bit lines. A column decode circuit prematurely couples a selected column to a data lead before a sense amplifier amplifies the data. This premature coupling is due to the increased operating speed at the 6.5 V supply voltage. Moreover, a second data amplifier is also activated prematurely due to increased operating speed and incorrectly reads the data on the data lead. Thus, an optimal design for normal operating conditions may fail a burn in test. A reduction in burn in conditions would result in an inordinate increase in burn in test time. Alternatively, a relaxation in circuit timing would greatly compromise circuit performance under normal operating conditions.